发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To decrease the number of parts by generating plural frequencies with plural voltage control oscillators, plural low pass filters, one programmable divider, one phase comparator, two switches and one controller by using the output voltage holding characteristic of a low pass filter. CONSTITUTION:When the leaking current of an LPF12 is made smaller and the output of a phi-DET 5 is made into a floating condition for about one second, the output frequency of VCO11 is hardly changed, and therefore, an f1=N1.fR stable frequency is outputted from the VCO11. In the same way, the leak current of an LPF29 is made smaller and a PLL including the VCO11 and the PLL including a VCO28 are alternately switched by the frequency-dividing ratio of SW13, SW26 and PD4, for example, every one second or less. Thus, different frequencies f1 and f2 can be simultaneously generated with one PD, one phi-DET, two switches and a controller.
申请公布号 JPS63209223(A) 申请公布日期 1988.08.30
申请号 JP19870043346 申请日期 1987.02.25
申请人 NEC CORP 发明人 ICHIKAWA MASAOMI
分类号 H03L7/22 主分类号 H03L7/22
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