| 摘要 |
PURPOSE:To decide it as a collation error when 0s are consecutive for (m) times or above by inverting the logic output of the detection means in the state of a failure where the same logic value of a pseudo random signal is consecutive more than m-number of times. CONSTITUTION:When a random code 10 is inputted at every clock 11 to the (m-n)-stage, the output of the m-stage shift register 6 is 0 so long as 0s are not consecutively more than (m) times in the random code input because the clear input of the register 6 is active. When 0s are consecutive for (m) times or above to the random code input, no clearing is applied to the register 6 and 1 is outputted from the register 6. In this case, since the output of a 1st exclusive OR gate 3 is 0, the output of a 2nd exclusive OR gate 7 is 1 and the output 12 of a 3rd exclusive OR gate 4 goes to 1, to apply error detection.
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