| 摘要 |
PURPOSE:To decrease the bit number of an output without deteriorating the S/N by applying subsequent connection to delta sigma quantizer of multiple integration (more than double integration) as unit stage. CONSTITUTION:A double integration delta sigma quantizer 61 uses the 1st integration device 25 so as to integrate an input signal 13 and uses the 2nd integration device 26 for further integration. It is discriminated by a comparator 35, and the binary signal output is fed back negative to the input of the integration devices 25, 26 to provide the double integration noise suppression characteristic. Thus, the triple integration noise suppression characteristic is provided together with the 1st and 2nd stage integrations. Then as to the output level number, the 1st stage output Y1 and the 2nd stage output Y2 take binary values of +1, -1. Moreover, the delay output Y2' of the Y1 takes tow-value of +1, -2, the differentiation output Y2' takes tristate values of +2, 0, -2, and its summing output Y4 takes 4-value of 3, 1, -1, -3. Thus, the output level number is halved.
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