| 摘要 |
<p>SERIAL-TO-PARALLEL CONVERTER FOR HIGH-SPEED BIT STREAMS A serial bit stream and a clock signal at a frequency equal to the bit rate divided by an integer n are passed in opposite directions via respective delay lines to respectively the data and clock inputs of n flip-flops, which thereby each latch a respective one of n bits of the bit stream during n/2 bit periods. During the next n/2 bit periods the outputs of the flip-flops are stable, and the n bits are latched in d parallel data latch. The delay lines comprise transmission lines terminated with their effective characteristic impedances. The converter is particularly useful for bit rates greater than lGb/s.</p> |
