| 摘要 |
PURPOSE:To eliminate the necessity of designing and verifying a periphery of each type of the title device at the time of its development as a periphery region for a gate array and to improve the development efficiency by using the periphery as a macro periphery. CONSTITUTION:A periphery region 2 for laying out input/output interface for connecting a semiconductor chip 1 to an external circuit and a common pattern is constructed to utilize a periphery all developed for a gate array as it is. Different function blocks at each type and its macro section are laid out in an internal block region 3. Thus, a designer may design only the layout of the region 3 to remarkably improve the development efficiency. |
