| 摘要 |
PURPOSE:To lower data transmission frequency between an image processor and a display device by sequentially and serially writing inputted video data in video memories and simultaneously reading out the data from the video memories in parallel. CONSTITUTION:In the video processor 10, the inputted video signal is sequentially and serially written in the video memories 20 and 22 through an A/D converter 16 by the synchronizing signal of a timing generator 18. On the other hand, the data is read out from the video memories 20 and 22 in parallel. Then, the data read out from the memories 20 and 22 in parallel is transmitted to the display device 12 through a transmission line 14 in parallel. Therefore, the read out speed can be lowered. Thus, the data transmission frequency between the image processor and the display device can be lowered.
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