FLAG GENERATING CIRCUIT

摘要

PURPOSE:To detect at high speed the all '0' and all '1' of the arithmetic result by carrying out simultaneously plural pairs of logic operations for four bits adjacent to each other of two arithmetic input data A and B. CONSTITUTION:An addend and an augend are stored in an X register 114 and a Y register 115 of an arithmetic unit 100 and an arithmetic operation is carried out. The augend is supplied to a complement circuit 112 from the register 115 for the execution of adding/subtracting operations. An adder 111 has an carry transmission circuit and holds a generated carry flag in a carry holding FF. A zero flag generating circuit 110 detects whether the arithmetic result of the adder 111 is is equal to all '0' or not before reception of the output result of the adder 111. Then the circuit 110 is actuated independently of the adder 111 so that a zero flag is obtained earlier than the arithmetic result.