Squared-radix discrete Fourier transform

摘要

A radix-N2 or radix-N4 discrete Fourier transform (DFT) processor having cascaded stages alternately comprising N2-sample memories and radix-N DFT's. Data is written into and read from the memories in a sequence permitting data to be written into a memory address immediately after the previously stored data is read from the same memory address, thereby avoiding the need for double-buffered memory. In one embodiment of the invention, two radix-N2 processors are cascaded to produce a radix-N4 DFT processor with even greater memory savings.