| 摘要 |
PURPOSE:To inhibit an internal interruption in the course of a step operation by masking an interruption control flag in a status register of a saved target CPU, by a system CPU. CONSTITUTION:At the time of executing a step operation, first of all, an interruption control flag in status register information of a target CPU 11 saved already in a bidirectional memory 6 is further saved in a system memory 3 by a system CPU 1. Subsequently, under the control of the target CPU 11, an instruction code to be executed is stored in the bidirectional memory 6 from a target memory 12. Moreover, by the system CPU 1, this instruction code is saved to the system memory 3 from the memory 6. Thereafter, the interruption control flag stored in the bidirectional memory 6 is masked by the system CPU 1, and a step operation to which an interruption is inhibited is executed by a monitor program 7. |
