发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To decrease the capacity of a RAM by providing a decoder for decoding an address stored in an address storing means and outputting a bit of modification information for modifying write information and an arithmetic instruction. CONSTITUTION:The RAM 1 is a RAM to which a microcomputer can execute read-out and write. A register 2 holds a bit of information to be written to the RAM 1 inputted through an input line 10. An address register 3 holds an address to execute read-out and write of the RAM 1 inputted through a signal line 11. A decoder 4 is controlled as to whether it is effective or ineffective by the operation mode of an information processor, decodes the address of the RAM 1 which the address register 3 holds, and outputs a data corresponding to this address and an arithmetic instruction. An arithmetic circuit 5 inputs the information of the register 2 and the data from the decoder 4, executes an arithmetic operation based on the arithmetic instruction outputted from the decoder 4, and writes its result to the RAM 1.
申请公布号 JPS63208142(A) 申请公布日期 1988.08.29
申请号 JP19870041786 申请日期 1987.02.25
申请人 NEC CORP 发明人 NOGUCHI TAKAYUKI
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
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