DIGITAL PROCESSORANORDNING ANORDNAD FOR PIPELINE-DATABEHANDLINGSOPERATIONER

摘要

A pipelined digital processor includes control circuits which during a first processor cycle decode a single conditional instruction for controlling performance of a specific condition test during the next (second) processor cycle and decode another instruction word during the second processor cycle for controlling all processing section operations during the subsequent (third) processor cycle. A circuit performs the condition test by comparing conditions existing in the digital processor during the second processor cycle with the specific condition information included in the conditional instruction for selectively disabling control of at least one section of the digital processor during the third processor cycle depending on the result of the condition test. As described the processor is a multiplier using Booth's algorithm. The pipelined sections include a multiplier forming succcessive partial products, an accumulator accumulating those products, and a rounding circuit to round the accumulated product.