发明名称 DYNAMIC RAM
摘要 PURPOSE:To shorten the cycle time of a partial writing action with the simple control by reading continuously the 4-byte data in four times with a RAS signal kept as it is and writing the merge data by two times through four times with the falls of the CAS and WE (write enable) signals. CONSTITUTION:It is allowed to read data of 16 bytes in all (4 bytes each time) out of a memory matrix circuit 25. Then the CAS and WE signals are produced continuously in 2, 3 or 4 times in response to 8, 12 or 16 bytes of a part related to a partial writing action. Then the RAS signal is reset finally. The data of 8, 12 or 16 bytes received from a host device is merged with the data of maximum 16 bytes read out of the circuit 25. At the same time, these merged data are written into the circuit 25 according to the CAS and WE signals. Thus the cycle time can be shortened with the simple control.
申请公布号 JPS63206993(A) 申请公布日期 1988.08.26
申请号 JP19870039637 申请日期 1987.02.23
申请人 NEC CORP 发明人 TAKISHIMA TORU
分类号 G11C11/401;G06F12/02;G06F12/04;G11C11/34 主分类号 G11C11/401
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