发明名称 DYNAMIC RAM
摘要 PURPOSE:To realize a high density state for a large capacity memory by setting two bit lines opposite to a single sensor amplifier. CONSTITUTION:Two bit lines are divided into three parts respectively and the sense amplifiers are provided at two dividing points of each divided bit line. While three word lines are provided with each divided block (9 pieces in all). The memory cells 201-218 are all set at the intersecting points between the bit and word lines. The bit lines 401 and 404 are connected to a sense amplifier 101; while the bit lines 403 and 406 are connected to a sense amplifier 102 respectively. A single sense amplifier can be provided every two bit lines like a return type bit line system with use of a memory cell of an open type bit line system where memory cells exist at all intersecting points between word and bit lines. Thus it is possible to obtain a dynamic RAM which is advantageous to realize a high density state of a large capacity memory.
申请公布号 JPS63206991(A) 申请公布日期 1988.08.26
申请号 JP19870039419 申请日期 1987.02.23
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 INOUE MICHIHIRO;YAMADA TOSHIRO
分类号 G11C11/401;G11C11/34;H01L21/8242;H01L27/10;H01L27/108 主分类号 G11C11/401
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