| 摘要 |
PURPOSE:To improve the address setting time characteristics at the time of a writing action by delaying the change to an active state from a non-active state and setting the change to a non-active state from an active state only at the delays of an input buffer circuit and a NAND circuit. CONSTITUTION:A signal changing to an active state from a non-active state is slower by a delay time set by a delay circuit than a signal changing to a non-active state to an active state among those output signals of an address buffer circuit. Thus the generation of a simultaneous active period can be solved in a terms of a circuit constitution for the output signals of the address buffer circuit. While the timing delay of an OFF state of a column gate can be eliminated since the change to a non-active state from an active state is limited just to the delays of an input buffer circuit and a NAND circuit. Thus the address setting time characteristics can be improved.
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