| 摘要 |
PURPOSE:To reduce the quantity of hardwares, by supplying a data with the same value as that of a set data on a key register to the input on the other side of a comparator at the time of setting a key word on the key register. CONSTITUTION:At the time of retrieval, the key value of the key register 201 is set as input to the one side of the comparator 203, and the output 172 of the key register is supplied to the input on the other side of the comparator 203 as a data targeted to be retrieved. And when both data coincide and also a comparison result signal 151 in a front stage cell is 1, the AND condition of an AND circuit 205 is satisfied, then, an FF207 goes to 1. The output 152 of the FF207 is transferred to a cell at the next stage as the comparison result signal. Meanwhile, when a fault is generated in the register 201, the value of the output 204 of the comparator 203 is 0, and a signal 209 inverted by an inverter 208 goes to 1. And an AND gate 210 is satisfied in a period where a decode signal 132 is 1, and 1 is outputted to a fault detecting line 162. In such a way, it is not required to prepare a redundant bit or a checking circuit on each key register. |
