| 摘要 |
<p>Improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors (24, 26), respectively, separated by clocked inverters (20). The circuit employs a single clock signal (CK) to synchronize the dynamic logic operations of said logic gates and, along with a second, complement clock signal (CK), said clocked inverters (20). Precharge transistors (28, 30, 32, 34) of each conductivity type are slowed slightly with respect to logic transistors (24, 26), and the complement clock signal is delayed slightly with respect to the clock signal, thereby providing racefree logic operations. An inplementation in a PLA is disclosed employing two logic planes (10, 12) for implementing arbitrary logic equations on input logic signals (14). The first logic plane (10) and second logic plane (12) are evaluated on separate phases of a complement clock signal (CK) and are separated by a clocked latch/inverter (20) for providing correct logic evaluation between the logic planes.</p> |
