发明名称 |
PROCESS FOR MANUFACTURING A MOS INTEGRATED CIRCUIT EMPLOYING A METHOD OF FORMING REFRACTORY METAL SILICIDE AREAS |
摘要 |
A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device. |
申请公布号 |
DE3472860(D1) |
申请公布日期 |
1988.08.25 |
申请号 |
DE19843472860 |
申请日期 |
1984.08.09 |
申请人 |
TEKTRONIX, INC. |
发明人 |
PARK, HEE KYUN;YAMAGUCHI, TADANORI |
分类号 |
H01L27/088;H01L21/266;H01L21/28;H01L21/76;H01L21/762;H01L21/763;H01L21/8234;H01L21/8238;H01L29/45;H01L29/49;H01L29/78;(IPC1-7):H01L21/76;H01L21/31;H01L21/82;H01L27/08 |
主分类号 |
H01L27/088 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|