| 摘要 |
A fast pull-in phase synchronizing circuit, including a phaselock loop, having an extended pull-in range. The phase synchronizing circuit includes, besides a conventional phaselock loop, at least a pi /2+n pi (n being an integer) phase shifter, a mixer, a low pass filter and another mixer. The phase shifter receives the output of the phaselock loop VCO, the output of the phase shifter being multiplied in the mixer with the circuit input signal. This multiplied signal is applied as an input to the low pass filter, which produces a low frequency output proportional to the frequency difference between the input and output signals. This low frequency signal is mixed in the other mixer with the circuit input signal to produce the phaselock loop input signal. The phaselock loop input is phase compared with the VCO output in the phaseback loop phase comparator. This phase comparator output has by reason of the phase synchronizing circuit of the invention two components, one representing the frequency discrimination characteristic of the circuit, the other the phase comparison characteristic. When in its unsynchronized state, the circuit of the invention operates as an automatic frequency control circuit causing the VCO oscillating frequency to vary in a direction to decrease the frequency error, Win-Wont. Once the frequency error has been reduced to the pull-in range, i.e. the synchronized range, the circuit of the invention operates to produce phase synchronization. |
