| 摘要 |
PURPOSE:To shorten and decrease the whole logical simulation time by providing an instruction execution control pseudo procedure for detecting the time for switching an operation mode for executing an instruction, between a logical simulator and an instruction execution control procedure while an I/O instruction is being executed. CONSTITUTION:The titled device is provided with an instruction execution control pseudo procedure 8 for detecting the time for switching an operation mode for executing an instruction, between a logical simulator and a communication routine 3. In this state, in case of executing a test program for testing an input/output (IO) instruction, the logical simulator 2 executes the IO instruction, and an operation for waiting for an end report of an IO operation started by the IO instruction, and the instruction execution control pseudo procedure 8 executes an operation of other CPU system instruction. Accordingly, in a logical simulation operation for testing the IO instruction, when data of an input/output processor model (IOP) 6 and an input/output device mode 7 are being transferred, a central processor model 5 can wait for an IO instruction from the OP 6 based on the end of a data transfer without executing an instruction at all. In such a way, the logical simulation time can be shortened and decreased. |
