| 摘要 |
PURPOSE:To shorten a testing time, by providing a circuit, which forcibly clamps the output level of an output buffer to '1' and '0' on the basis of the control input signal from the outside regardless of the state of the internal logic circuit in an integrated logic circuit, in an output buffer circuit. CONSTITUTION:P-channel MOSFETs 4-6 and N-channel MOSFETs 7-9 are combined to provide three stages of output buffer circuits B1-B3 and, further, an output '1' clamp circuit C1 using P-channel MOSFET 12 and N-channel MOSFET 14 and an output '0' clamp circuit C2 using P-channel MOSFET 13 and N-channel MOSFET 15 are provided to the circuits B1, B2. In the test of an integrated logic circuit using this output buffer circuit, the characteristic of an output terminal 2 is tested but, in this case, when the control terminal 10 of the output '1' circuit C1 is brought to a low level regardless of the state of an internal logic circuit, output can be forcibly set to '1' and, when the control terminal 11 of the output '0' circuit C2 is brought to a low level, output can be forcibly set to '0'.
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