发明名称 CLOCK SIGNAL SWITCHING CIRCUIT
摘要 <p>PURPOSE:To decrease the number of component parts of a clock signal switching circuit and to simplify the circuit constitution, by using two 2-input data selectors, two fall edge trigger type FF circuits, and a single 4-input data selector. CONSTITUTION:When 'H' of a clock selection signal S is supplied, the output signals (e) and (f) of the FF 13 and 14 are set at 'H' and a clock signal A is delivered to an output terminal 10 of a 4-input data selector 15. At the same time, the signals (a) and (b) of the same types as clock signals A and B are delivered to the outputs Y of 2-input data selectors 11 and 12 respectively. When the signal S is changed to 'L', the FF 13 is sampled at the fall edge of the signal (a). Then the signal (f) is set at 'L' and the signal B is delivered to the terminal 10. Thus a switching action is through between signals A and B. As a result, the number of FF circuits can be decreased and the constitution of a clock signal switching circuit is simplified.</p>
申请公布号 JPS63204425(A) 申请公布日期 1988.08.24
申请号 JP19870035691 申请日期 1987.02.20
申请人 MITSUBISHI ELECTRIC CORP 发明人 EURA FUMIAKI
分类号 G06F12/00;G06F1/04;G06F1/06 主分类号 G06F12/00
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