发明名称 SIGNAL LEVEL CLAMPING CIRCUIT
摘要 PURPOSE:To remove an offset voltage, including the one produced from a signal processing circuit itself, and to set a highly precise signal level setting by giving a feedback to the output signal of the signal processing circuit, after converting it to a digital signal, and clamping the voltage level of the input signal of the signal processing circuit. CONSTITUTION:A clamping voltage is adjusted based on a digital voltage quantity, outputted from the signal processing circuit to process the input signal. Namely, the digital quantity of the voltage, outputted by the signal processing circuit, and a digital code, corresponding to the target reference voltage level are compared by a comparator 11, and the digital quantity corresponding to their difference voltage is outputted. Next, the digital quantity is converted into an analog quantity V10 by a D/A converter 12, and further, the analog voltage quantity V10 is added or subtracted during the specified period of the input signal. As the result of the addition or the subtraction of the first time, when the difference voltage appears still in the output of the comparator 11, the clamp voltage quantity V8 is corrected by giving the further feedback. Thus, the feedback is given until the difference voltage comes to zero substantially. Thus, the setting of the highly precise clamp voltage is made possible.
申请公布号 JPS63204975(A) 申请公布日期 1988.08.24
申请号 JP19870037613 申请日期 1987.02.20
申请人 FUJITSU LTD 发明人 KOBAYASHI OSAMU;GOTO KUNIHIKO
分类号 H04N5/18 主分类号 H04N5/18
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