| 摘要 |
PURPOSE:To sharply reduce a memory array and a chip area by arranging memory cells on the intersecting points between word lines and digit lines and arranging 1st and 2nd sense amplifiers adjacently between two pairs of digit lines in the direction. CONSTITUTION:The cells are arrayed by an open digit line system and the 1st and 2nd sense amplifiers 31, 32 are adjacently arranged between two pairs of digit lines D11, D01 and D12, D02 with a fixed interval in the line direction. When a pair of memory cells 11, 21 connected to a 1st pair of digit liens D11, D01 are selected, a signal from one cell 11 is inputted to the 1st sense amplifier 31 and a signal from the other cell 21 is inputted to the 2nd sense amplifier 32 arranged adjacently to the amplifier 31 through a 2nd wiring 5. Consequently, the cells can be arrayed furthermore with high density, and since only one sense amplifier is arranged in the layout pitch of two digit lines, the area of the whole memory array can be reduced.
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