Reference potential generating circuit for a semiconductor device.

摘要

A plurality of dummy cells forming a dummy cell array is formed in the semiconductor chip (100). A dummy cell (32) surrounded by other dummy cells in the array is used for generating a reference potential. The contact (282) of Vss line for connecting the source of the dummy cell to the ground is located at the center portion of the dummy cell array. With such a layout, the cell pattern of the dummy cell is the same as that of the memory cells. Accordingly, the transistor characteristics of these cells may also be substantially identical to each other. Thus, the problem arising from the difference in the pattern geometry can be solved.