Reconfigurable counters for addressing in graphics display systems.

摘要

In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter in performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a second predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reaching to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.