发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To enable TAT to be shortened by a method wherein the checking processes of misalignment of masking as well as the requirements for exposure and development are performed using a specified check pattern in the same position. CONSTITUTION:During the checking process of misalignment of masking, the checking processes of misalignment as well as the requirements for exposure and development are to be performed using a specified check pattern arranged in the same position. In other words, when the length l1 of pedestal patterns 1, 2 is specified to be equivalent to the design dimension of mask applied to form resist patterns 11, the requirements for exposure and development can be judged to be adequate if l1=l11 comparing the length l11 of resist pattern 11 with the length l1 while to be inadequate if l1 and l11 are markedly different from each other.
申请公布号 JPS63204721(A) 申请公布日期 1988.08.24
申请号 JP19870038171 申请日期 1987.02.20
申请人 NEC CORP 发明人 OMI SATORU
分类号 H01L21/68;H01L21/027;H01L21/30 主分类号 H01L21/68
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