发明名称 TESTING EQUIPMENT FOR A/D CONVERTER
摘要 PURPOSE:To reduce the test time by providing a gate control means generating a gate signal controlling a memory so as to store a conversion data from a zero code to a full code based on the zero code and the full code detection signal of a conversion data outputted from an A/D converter being an object of measurement. CONSTITUTION:A gate control circuit 9 detects that a output code of a conversion data D of an A/D converter (DUT)4 being an object of measurement changes from zero to zero+1 or from full to full-1 to start the storage of the data D to a memory 5, detects that the output code of the conversion data D of the DUT 4 changes again zero or full to output a gate signal SG to complete the storage of the data D into the memory 5. A prescribed arithmetic processing is applied to the data D stored in the memory 5 in this way to obtain the result of test of the DUT 4. Thus, the level adjustment of a sinusoidal wave signal fed to the DUT 4 is not required and the test time is reduced.
申请公布号 JPS63204820(A) 申请公布日期 1988.08.24
申请号 JP19870036401 申请日期 1987.02.19
申请人 YOKOGAWA ELECTRIC CORP 发明人 MACHIDA AKIHARU
分类号 H03M1/10 主分类号 H03M1/10
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