Arithmetic logic circuit having a carry generator

摘要

An inverting full adder circuit for use in a ripple-carry adder or arithmetic logic unit (ALU) which includes a plurality of similar full adder stages connected in series such that the carry delay from one stage to the next is minimized, and which requires fewer devices and less space on the surface of a semiconductor chip than do known adders or ALUs of comparable performance. This invention may use either N-channel field effect transistors, i.e., NMOS technology, or it may use complementary metal oxide semiconductor (CMOS) technology.