发明名称 |
Methods for fabricating latchup-preventing CMOS device |
摘要 |
A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 mu m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
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申请公布号 |
US4766090(A) |
申请公布日期 |
1988.08.23 |
申请号 |
US19860933631 |
申请日期 |
1986.11.21 |
申请人 |
AMERICAN TELEPHONE AND TELEGRAPH COMPANY, AT&T BELL LABORATORIES |
发明人 |
COQUIN, GERALD A.;LYNCH, WILLIAM T.;PARRILLO, LOUIS C. |
分类号 |
H01L21/763;(IPC1-7):H01L21/425 |
主分类号 |
H01L21/763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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