发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT WITH TESTING MECHANISM
摘要 PURPOSE:To curtail necessary memory capacity, by placing a compression mechanism of information on results of test in front of an expected value collating section. CONSTITUTION:A control signal is inputted from a control signal input terminal 11 to operate selectors 4-1 and 4-2 with a controller 8, a circuit 3 to be tested is separated from an internal circuit 2 to fetch a test signal involved from a test signal generating memory section 7 and the signal is supplied to a circuit through the selector 4-1 to implement a function test. Then, the results of testing are inputted into a check sum generation circuit 13 through the selector 4-2 to weight (n) input signals as grouped by the number (m) and output signals are cut down to the number n/m to be inputted into an expected value collating section 5. The collating section 5 collates said output signals with a check sum expected value for the results of testing previously taken out of an expected value memory section 6 with the controller 8 and the results are outputted with an expected value collation results output terminal 12. Thus, necessary memory capacity can be curtailed.
申请公布号 JPS63204170(A) 申请公布日期 1988.08.23
申请号 JP19870036454 申请日期 1987.02.18
申请人 NEC CORP 发明人 ITO JUN
分类号 H01L21/66;G01R31/28;H01L21/822;H01L27/04 主分类号 H01L21/66
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