| 摘要 |
PURPOSE:To demodulate an input data in parallel simultaneously by converting an input data comprising a serial data inputted sequentially into a parallel data having an input data for reference before and after the data. CONSTITUTION:An input M<2>FM data DMM is converted into 4-bit M<2>FM data M<0>, M<1>, M<2> and M<3> by a serial/parallel conversion circuit 2. Then, the data is subject to parallel processing by 2-bit each according to the NRZ system format, the NRZ data NRZ0, NRZ1...NRZ6, NRZ7 by 8-bit are latched in the four period of the 1st clock CK2 and demodulated into a serial NRZ data DN by a parallel/serial conversion circuit 10. Since the parallel processing circuit part is constituted by using logic circuits having a slow processing speed, the power consumption is reduced remarkably.
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