| 摘要 |
PURPOSE:To reduce the intervention of a software by transferring a data in the unit of blocks between a line adaptor and a memory and generating an interruption at every prescribed character transfer. CONSTITUTION:A character on a bus 47 is stored in a transmission buffer 13 in a transmission buffer control circuit 15, a start/stop bit is added and a data is outputted serially from a transmission line 31. A serial input data from a reception line 32 is converted into a parallel character by a serial/ parallel conversion circuit 12 and transferred to a reception buffer 14. A DMA controller 5 writes a character on a bus 47 to an address of the memory 3 represented by a reception address register RaAR, increments the content of the RaAR by 1 and decrements the content of a reception count register RxCR by 1. When the content of the RxCR is zero, a DMA controller 5 uses the automatic load function, transfers the content of the reception base address register to the RxAR, RxCR and the CPU 4 calculates an idle capacity of the input buffer area on the memory 3.
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