发明名称 SERIAL DATA RECEPTION CIRCUIT
摘要 PURPOSE:To eliminate the need for the software processing for data comparison by storing the result of comparison between a preceding data of a present data and a data by two preceding time and comparing the both. CONSTITUTION:A D flip-flop 7 acts like a means storing the result of comparison of one preceding data of the present data by a bit comparison circuit 5. Moreover, when a start control signal transfers to a high level, it is triggered to fetch an output at an output terminal Q2 of the D flip-flop 6. Thus, a data by further preceding time as to the data of one preceding time is compared and its result is stored as to the data stored as the output of the D flip-flop 6. Only when the result of comparison of the present data is identical and the result of comparison of the data of one preceding time is dissident, the output of an AND gate 8 goes to a high level. Thus, whether or not two consecutive data are identical is discriminated.
申请公布号 JPS63202148(A) 申请公布日期 1988.08.22
申请号 JP19870034098 申请日期 1987.02.17
申请人 SANYO ELECTRIC CO LTD 发明人 KON YOSHIHIKO;YAMASHITA NORIO
分类号 H04L1/08;G06F13/00 主分类号 H04L1/08
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