发明名称 ERROR CORRECTION AND DECODING METHOD
摘要 PURPOSE:To decrease number of arithmetic circuits by using a BCH code so as to calculate the syndrome and applying the calculation of conversion to each coefficient only in the calculation of a conversion equation such as A(x) in obtaining an error location polynomial or the like. CONSTITUTION:The number of arithmetic operations to calculate conversion equations of A(x), L(x), B(x) and M(x) at once is respectively multiplications of (degB+1) times, (2t-degA+1) times, (degA+1) times and (2t-degB+1) times (t is the maximum number of correctable errors for the code) and additions of the same number of times respectively. The largest number of times of the arithmetic operations is 4t<2>+3t times for both the multiplication and the addition. In this invention, since only each coefficient is subject to conversion calculation in the equations, the total number of times of arithmetic operations obtained for the largest number of times is reduced from 18t<2>+6 in a conventional number into 8t<2>+6t times. Thus, an inexpensive exclusive processor with a fast operating time is used.
申请公布号 JPS63203018(A) 申请公布日期 1988.08.22
申请号 JP19870034643 申请日期 1987.02.19
申请人 MATSUSHITA COMMUN IND CO LTD;MATSUSHITA ELECTRIC IND CO LTD 发明人 KATO OSAMU;IWAKUNI KAORU
分类号 H03M13/00;G11B20/18 主分类号 H03M13/00
代理机构 代理人
主权项
地址