发明名称 INTER-FRAME PREDICTIVE DECODER
摘要 <p>PURPOSE:To prevent an error in a decoded image even if an interframe predicting decoding error takes place by providing a switching signal generating circuit, 1st and 2nd frame memories and a selector circuit. CONSTITUTION:An inter-frame predictive decoding error 13 takes place in three frames x3-x5 of an inter-frame prediction composite signal 12 and the error is lost after the frame x6 and its subsequent frames. A frame memory output 14 is delayed for one frame time with respect to the signal 12 and outputted in the order of x1, x2, x3-. A switching signal 17 goes to a H level in the normal state and goes to a L level only a frame just after that having the error 13. When the signal 17 is at the H level, a selector circuit 104 selects the output 14 and when at the L level, a frame memory output 16 is selected. Thus, when the error 13 takes place, the output 14 of the preceding frame x2 is outputted and when it is lost, the output x6 at that time is outputted as it is. Thus, the output 16 is delayed by one frame time and outputted as shown in figure. Thus, even when the error 13 takes place, no error is caused in the decoded image.</p>
申请公布号 JPS63203078(A) 申请公布日期 1988.08.22
申请号 JP19870034603 申请日期 1987.02.19
申请人 NEC CORP 发明人 YASUDA TORU
分类号 H04N19/50;H04N19/102;H04N19/166;H04N19/423;H04N19/44;H04N19/503;H04N19/59;H04N19/65;H04N19/70;H04N19/85;H04N19/89;H04N19/895 主分类号 H04N19/50
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