发明名称 VERTICAL SYNCHRONIZING SEPARATOR CIRCUIT
摘要 PURPOSE:To accurately separate a vertical synchronizing signal with simple constitution by restoring forcibly an output signal of an RC time constant circuit when the pulse width is narrower than the RC time constant regardless of the upward/downward input pulse so as to completely eliminate a pulse narrower than the RC time constant. CONSTITUTION:Both an input signal A and an /output signal C' in the initial state are at logical 'L' and coincident with each other, and a transmission gate (TG)6 is turned on. Since the pulse A is discident with the output C' when the input pulse A rises, the TG 6 is turned off, an output integration signal B' of the RC time constant circuit rises, but when the pulse width is narrow, the pulse rises till the level does not reach the transition point of the inverter 3, the TG 6 is turned on and the integration signal B' is retracted again to the output C'. When the pulse width is wide, the level reaches till the transition point, the inverters 3, 4 are inverted and the output C' is inverted. As a result, both the input A and output C' are coincident at logical 'H', the TG 6 is turned on and the integration signal B' is locked to the output signal C', the output C' is inverted and the new initial state is attained and the downward thin pulse is erased.
申请公布号 JPS63202185(A) 申请公布日期 1988.08.22
申请号 JP19870034216 申请日期 1987.02.17
申请人 CITIZEN WATCH CO LTD 发明人 SUZUKI FUMINORI
分类号 H04N5/10 主分类号 H04N5/10
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