| 摘要 |
PURPOSE:To inhibit the generation of a large current, and to relax the deterioration of an input/output switching circuit by setting a phase difference of first and second timing pulses, to a value for absorbing a variance of a delay time of a memory and a data processing circuit, and eliminating a time zone in which both of them become an output state. CONSTITUTION:A pulse generating circuit 30 generates the first timing pulse 33, but a delaying circuit 31 outputs an intermediate timing pulse 34 which has delayed the first timing pulse 33 by a phase difference DELTAt. An AND circuit 32 brings the first timing pulse 33 and the intermediate timing pulse 34 to AND operation and outputs the second timing pulse 35. Accordingly, as for the second timing pulse 35, a phase difference DELTAt whose pulse width is narrower by 2DELTAt than the first timing pulse 33 is set to a value for only absorbing a variance of each delay time of a RAM 2. As a result, at the time of writing a data, a time zone in which both a buffer circuit 16 and an output side buffer circuit in the RAM 2 function is eliminated, and the generation of a large current can be obstructed.
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