| 摘要 |
PURPOSE:To reduce a necessary physical quantity by using hardware inherent to a computer and performing invariably secure time-out detection. CONSTITUTION:For example, a selection signal SEL0 has a logical level 1 while other selection signal has a logical level 0, and a TOD (time of Day) timer 1 is in a stop mode. At this time, a repetitive pulse signal at every 1ms period is outputted from an OR circuit 8. When machine word instruction is executed normally and a BOP (operation start) signal is generated at the time interval of <=1ms, the output of a flip-flop FF1 over attain the logical level 1. When the TOD timer 1 stops, the OR circuit 8 outputs the repetitive pulse signal from an interval timer 2 at every interval of 3.3ms. When the BOP signal is generated at the time interval of <=3.3ms under said condition, the FF11 never outputs the logical level 1. |
