发明名称 FRAME ALIGNER
摘要 <p>PURPOSE:To decide the output frame phase whose delay is minimized automatically by using a phase at first fed with an output clock pulse after the point of time written with an input signal to a FIFO memory as an output frame phase with respect to an optional input signal frame phase. CONSTITUTION:In the first-in first-out (FIFO) memories 5-1-5-N, when an input signal is written from the head of the input frame the moment the input frame phase is detected, the input frame phase is detected as the output frame phase in all the FIFO memories 5-1-5-N. After the point of time when the input signal is written in the FIFO memories 5-1-5-N, the phase fed at first with the output clock pulse is used as the reference. Moreover, when an idle memory is detected in the FIFO memories 5-1-5-N, a read clock is stopped. Thus, the read phase with minimized delay is decided automatically.</p>
申请公布号 JPS63200639(A) 申请公布日期 1988.08.18
申请号 JP19870032348 申请日期 1987.02.17
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 OKUMURA YASUYUKI;HAYASHI KAZUHIRO;KAKINUMA TAKAMA
分类号 H04J3/06;H04L7/00 主分类号 H04J3/06
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