发明名称 CACHE MEMORY CONTROL METHOD
摘要 PURPOSE:To improve the processing capacity of a CPU by preparing two types of write-back system cache memories for both a user area and a system area and decreasing the quantity of data written into a main memory when caches are replaced. CONSTITUTION:When a process where a processor 1 has a processing job is set in a system mode, a system deciding device 5 decides the mode of the processor 1 and actuates a system area cache memory 4 to send the data corresponding to the value of a physical address bus delivered from a memory control unit 2 back to the processor 1. At the same time, a swap-out controller 6 swaps out the latest memory data of a cache memory area 3 to a main memory 7. When the processor 1 performs its processing job in a user mode, the memory 3 is actuated to swap out the data on the memory 4 to the memory 7.
申请公布号 JPS63200251(A) 申请公布日期 1988.08.18
申请号 JP19870033062 申请日期 1987.02.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMADA KAZUMI
分类号 G06F12/08 主分类号 G06F12/08
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