发明名称 TELEVISION RECEIVER
摘要 PURPOSE:To make the titled receiver immune to the fluctuation of an input composite video signal and the fluctuation of a power voltage by providing separately a clock generator for write control of a pattern memory and a clock generator for read control. CONSTITUTION:In a television receiver applying video signal processing and synchronizing deflection processing digitally provided with one pattern memory, the clock generator 10 for the write control of the one pattern memory 7 and the read control clock generator 20 are provided separately and the video signal processing and the deflection signal processing after the read of the memory are executed by using the clock oscillated independently of the input composite video signal. Thus, the effect of the input composite video signal is avoided and the clock generating circuit is simplified, then the titled receiver is made immune to the fluctuation of the power supply voltage.
申请公布号 JPS63200680(A) 申请公布日期 1988.08.18
申请号 JP19870031629 申请日期 1987.02.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IMAI KIYOSHI
分类号 H04N5/44;H04N5/45;H04N5/907 主分类号 H04N5/44
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