发明名称 DIGITAL SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To constitute various types of digital circuits by using a single unit chip containing a multiplication part and addition part singly or in plural combination. CONSTITUTION:An n-bit multiplier signal B and an n-bit multiplicand signal A are applied to a multiplication part 17, a delay circuit 12 and a selector via variable delay circuits 10 and 11 respectively. The selector 18 selects either one of outputs of the part 17 and circuits 12, 10 and 11 and applies it to an addition part 22. While a signal C to be added of (2n-1+alpha) bits selects either one of a delay circuit 20 which works to have an amount of delay equal to about an upper bit and a delay circuit 19 which delays equally the signal of each bit through a selector 21 and applies it to the part 22. The output of addition is delivered after selecting either one of a delay circuit 23 which delays equally the signal of each bit and a delay circuit 24 which works to obtain an amount of delay equal to a lower bit or so through a selector 25.
申请公布号 JPS59127171(A) 申请公布日期 1984.07.21
申请号 JP19830002044 申请日期 1983.01.10
申请人 SONY KK 发明人 IWASE SEIICHIROU
分类号 G06F7/00;G06F7/544;G06F17/10;H03H17/02;H04N9/64;H04N9/65 主分类号 G06F7/00
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