| 摘要 |
PURPOSE:To suppress the latchup of an FET by providing the same conductivity type high concentration regions in a predetermined well directly under a gate electrode wiring layer, and superposing a guard band region formed in a self- alignment to eliminate the separation of the guard band. CONSTITUTION:A CMOS inverter is formed of a P-well 1, N-well 2, a gate electrode wiring layer 4, P-type drain, source regions 5, 6, and N-type drain, source regions 7, 8. An N-type diffused layer 10 is formed as the same conductivity type high concentration region as the well in a predetermined well 2 directly under the layer 4 of this configuration. The layer 10 as the high concentration region is superposed on the region of the same conductivity type guard band 3 disposed in the well to eliminate the separation of the band 3, thereby suppressing a chargeup. |
