Nonvolatile memory protection.

摘要

A nonvolatile memory protection system for a microprocessor system having a common address bus, to which a nonvolatile memory is connected, interposes a controller connected to the common address bus between the commands generated by the microprocessor and the nonvolatile memory. The controller generates valid commands for the nonvolatile memory upon receiving a predetermined sequence of commands from the microprocessor, disabling the nonvolatile memory in the absence of valid commands. A power protect circuit connected between the microprocessor system power supply and the nonvolatile memory provides a disable signal to the nonvolatile memory during power up and power down of the microprocessor system.