| 摘要 |
PURPOSE:To improve the frequency stability over a broad band by controlling a frequency division ratio of each variable frequency divider for a frequency shift keying (FSK) signal generating circuit and a PLL loop depending on the setting. CONSTITUTION:A reference signal from a reference oscillator 12 is processed by fixed frequency dividers 13, 14, 5, a variable frequency divider 6 and an LPF 7 to form a frequency shift signal, which is synthesized with a reference signal through the fixed frequency divider 10 and an LPF 11 by a frequency synthesizer 8, becomes an FSK signal subject to frequency modulation via a BPF 9 and fed to a phase comparator 19 of a PLL provided with the variable frequency divider 17 in the feedback loop. The frequency division ratio of the frequency divider 17 and the frequency divider 6 is controlled via an arithmetic unit 21 depending on the setting from a frequency setting input terminal 20 and the frequency shift of the frequency modulation wave is subject to automatic control corresponding to the output frequency. As a result, the frequency stability over the broad band is improve and the modulation characteristic is improved.
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