| 摘要 |
PURPOSE:To reduce the area of a chip by a method wherein, when the layout of a three-stage composite gate is to be designed, input signals, which are not the output of a second-stage gate out of the input of a third-stage gate, are input to a first gate and a second gate of a first-stage gate so that another two-stage composite gate can be constituted. CONSTITUTION:Input signals 1, 2, 5 are input to a first gate 7-3 of a first-stage gate 7a; input signals 3-5 are input to a second gate 7-4; a semiconductor integrated circuit having a three-stage logic gate is transformed into a two-stage structure. If a P-channel in a region B on the right of a well 12 is observed, the direction of the transverse axis which is parallel to the input signals is short; if an N-channel in a region A on the left of the well 12 is observed, the direction of the vertical axis which is perpendicular to the input signals is short; in addition, all the input signals 1-5 are spaced at equal intervals. By this setup, it is possible to reduce the area of a chip.
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