发明名称 CLOCK SWITCHING CIRCUIT
摘要 PURPOSE:To form a clock switching part with a low-speed process switching circuit by providing a dividing circuit and a multiplying circuit before and after the clock switching part respectively. CONSTITUTION:An input clock is usually selected within a clock switching part 2 and supplied to a data processing part 1 to be synchronous with the input data. When this information produces a no-input state or a frame step-out state, a switch control part signal is sent to a clock processing part 2 from the part 1 and a clock is selected out of a local oscillation part 4. This switching action forms a frame within an intermediate repeating installation and delivers data. Then an input clock dividing circuit 5 and a multiplying circuit 3b having the same value as the dividing ratio of the circuit 5 are added to a clock switching circuit at the front and back sides of the part 2 respectively. As a result, the switching actions of high frequency clocks can be minimized and a clock switching action is carried out through a low-speed processing action.
申请公布号 JPS63197210(A) 申请公布日期 1988.08.16
申请号 JP19870030797 申请日期 1987.02.12
申请人 NEC CORP 发明人 MIURA MASANORI
分类号 H04L25/52;G06F1/04;G06F1/08;H03K5/00;H04B3/36;H04L7/00 主分类号 H04L25/52
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