发明名称 MEMORY DEVICE CONTROL SYSTEM
摘要 PURPOSE:To shorten cycle time by securing such a constitution that a request device sends a reading instruction discriminating signal together with a reading action requesting signal and a memory interrupts its action to give the busy signal produced after the reading action is started to a priority circuit when said reading instruction discriminating signal is detected. CONSTITUTION:The request control circuits 1 and 2 of requesting devices 100 and 200 send the reading instruction discriminating signals 20 and 21 together with the reading action requesting signals. The busy control circuit 5 of a memory 300 detects both signals 20 and 21 and therefore interrupts the application of the busy signals 29 and 30 produced after a reading action is started to a priority circuit 3. In such a way, the reading cycle can be shortened after the reading action and the overall throughput of a memory is improved.
申请公布号 JPS63197260(A) 申请公布日期 1988.08.16
申请号 JP19870030795 申请日期 1987.02.12
申请人 NEC CORP 发明人 TAKISHIMA TORU
分类号 G06F9/52;G06F12/00;G06F13/16;G06F15/16;G06F15/177 主分类号 G06F9/52
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