发明名称 SERIAL DATA TRANSFER SYSTEM
摘要 PURPOSE:To transfer a data of different bit length without adding a dummy bit by placing oppositely a shift register storing an instruction code, a decoder decoding the contents, to a shift register storing a data and a latch circuit storing the content. CONSTITUTION:An instruction code representing the kind and bit length of a data is transferred consecutively after the data. Thus, when the bit length of the instruction code is n-bit (n is a natural number), the instruction code is stored in a 1st stage n-bit of reception shift registers 4, 5 without fail at the time point of transfer end by a strobe signal. Thus, a decoder 6 decodes the n-bit information to select gate circuits 7-9 to pass the strobe signal. That is, the latch circuits 10-11 corresponding to the bit length of the data transferred serially are selected to store the data. Thus, the addition of the dummy bit is not required to receive the data different from the bit length, then the data is transferred by a required minimum time.
申请公布号 JPS63197151(A) 申请公布日期 1988.08.16
申请号 JP19870028291 申请日期 1987.02.12
申请人 HITACHI LTD;HITACHI VIDEO ENG CO LTD 发明人 IKEDA RYUICHI;TAKAHARA YASUAKI
分类号 H04L29/06;H04L7/04;H04L13/00;H04L29/08 主分类号 H04L29/06
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