发明名称
摘要 PURPOSE:To always limit the number of comparators to one regardless of the number of address registers by selecting one of plural address registers through a partial field of address information within a packet. CONSTITUTION:The packet address information is divided into two fields F1 and F2. The addres registers are selected in the field F1, and the field F2 is defined as an actual comparison address. It is also possible to divide the packet address information into >=3 fields to have address registers of various levels. That is, the packet address information is divided into at least 2 parts and the address registers are selected in one of those two fields. The information of the F1 is used to the input of a multiplexer M, and as a result one of (n) units of address registers, e.g., a register AR1 is selected. In this case, the address comparison is executed between the register AR1 selected at the multiplexer M and the field F2.
申请公布号 JPS6341260(B2) 申请公布日期 1988.08.16
申请号 JP19820216453 申请日期 1982.12.10
申请人 FUJITSU LTD 发明人 JINZAKI AKIRA
分类号 H04L12/56 主分类号 H04L12/56
代理机构 代理人
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